1. Field of the Invention
The present invention relates to a predecoder of a semiconductor memory device, and more particularly to a circuit for predecoding internal addresses in a semiconductor memory device, and the circuit has a function for controlling a signal output from an output stage thereof, thereby being capable of achieving an improvement in the utility thereof.
2. Description of the Related Art
Where there are a number of input addresses to be decoded, it is inefficient to simultaneously decode those input addresses. In order to improve the decoding efficiency, a predecoder is used. The predecoder is a circuit for previously decoding a portion of the input addresses to be decoded, for example, two or three input addresses.
An output from such a predecoder is applied to a main decoder so that it is completely decoded in the main decoder.
Where decoding is carried out in a sequential manner as mentioned above, it is possible to minimize the number of transistors to be used for the decoding, thereby reducing the design area.
Outputs from a predecoder, which are grouped for an address group, are independent from those grouped for other address groups. For instance, a group of predecodings, for example, four predecodings, generated after predecoding an address group including, for example, the 0-th and first addresses, are independent from those generated after predecoding another address group including, for example, the second and third addresses. From each independent predecoding group, only one predecoding is selected based on an input address.
In the case of conventional predecoders, predecodings have a logic "high" or "low" level for one selected input address while having an opposite logic level for the remaining input addresses.
For instance, where a predecoder is used which is adapted to predecode the second and third input addresses, predecodings output from the predecoder may be designated by "ax23&lt;0&gt;", "ax23&lt;1&gt;", "ax23&lt;2&gt;", and "ax23&lt;3&gt;", respectively.
If the predecoding "ax23&lt;0&gt;" corresponds to a selected output address, it is then output at a logic "high" level. In this case, the remaining predecodings "ax23&lt;1&gt;", "ax23&lt;2&gt;", and "ax23&lt;3&gt;" are output at a logic "low" level. Otherwise, the predecoding "ax23&lt;0&gt;" is output at a logic "low" level whereas the remaining predecodings "ax23&lt;1&gt;", "ax23&lt;2&gt;", and "ax23&lt;3&gt;" are output at a logic "high" level. In such a fashion, only one predecoding is selected for a selected output address.
However, such a predecoder is used for limited applications. In other words, it cannot be used in the case in which it is necessary to use an output signal having a logic level opposite to that of the output signal from the predecoder under a particular condition.
Generally, predecoders are frequently used in combination with a logic circuit.
For instance, a "redundancy use identifying circuit" is coupled to a predecoder in order to use an output from the predecoder.
Where there are defects or failures occurring in several cells in a semiconductor memory cell including a plurality of cell arrays due to a variety of reasons, it is necessary to replace those cells with repair cells in order to prevent a degradation in the throughput of the chip. To this end, the user inputs addresses designating those cells involving defects. In this case, the "redundancy use identifying circuit" is a circuit for identifying, in response to the addresses input by the user, whether or not the cells involving defects have been replaced with repair cells.
Such a redundancy use identifying circuit is physically recorded with address data associated with repair cells. The address data is always present in the redundancy use identifying circuit without being volatilized after a power cut-off.
For physical recording of address data, there are many methods including a recording method using fuses, a recording method using antifuses, and other various non-volatile recording methods.
Referring to FIG. 1b, a cell repair circuit using fuses is illustrated. In this cell repair circuit, a fuse corresponding to the address of a cell to be replaced with a repair cell is cut off.
When an address designating a cell to be replaced with a repair cell is input to the cell repair circuit, for instance, when input addresses "ax23&lt;0&gt;", "ax45&lt;1&gt;", and "ax67&lt;2&gt;" have a logic "high" level whereas the remaining input addresses have a logic "low" level, no current path is established between a node A and the ground, as shown in FIG. 1b. In this state, accordingly, the node A is maintained at a precharge potential level, namely, a high potential level. As a result, a signal nrd indicative of an address designating the repair cell is generated. Based on the signal nrd, a repair operation is then conducted.
In this case, the signal nrd has a logic "high" level.
On the other hand, when an address designating a normal cell requiring no replacement thereof, for instance, when input addresses "ax23&lt;1&gt;", "ax45&lt;1&gt;", and "ax67&lt;2&gt;" have a logic "high" level, at least one current path is established between the node A and the ground. In this state, the precharge voltage having a "high" potential level is coupled to the ground via the current path. As a result, the signal nrd indicative of an address designating the repair cell is not generated. In this case, a normal operation is conducted.
That is, the signal nrd has a "low" potential level.
In FIG. 1b, input addresses "ax23&lt;0:3&gt;", "ax45&lt;0:3&gt;", and "ax67&lt;0:3&gt;" are predecodings, namely, predecoded signals, output from a predecoder shown in FIG. 1a.
In the case of the cell repair circuit using fuses, as shown in FIG. 1b, the signal nrd indicative of an address designating the repair cell is generated only when all fuses cut off are selected. That is, the signal nrd is generated in accordance with an ANDing operation for programmed (namely, cut-off) fuses.
Referring to FIG. 2, a cell repair circuit using antifuses is illustrated.
An antifuse is a device having a function opposite to that of a fuse. That is, such an antifuse has characteristics of an electrical connection when being programmed. The antifuse has a basic configuration similar to a capacitor. When such an antifuse is programmed, an insulating layer included in the antifuse collapses, thereby causing the antifuse to be rendered in an electrical connection state.
Where antifuses are used in the fabrication of semiconductor devices, it is possible to reduce the area for fuses. Those semiconductor devices can be also repaired even in a packaged state. The reduction of the fuse size expected by virtue of the use of antifuses can be achieved proportionally to the size reduction for other semiconductor device parts.
The operation of the cell repair circuit using antifuses will now be described in conjunction with FIG. 2.
In an initial precharge state, a node A in the cell repair circuit of FIG. 2 has a "high" potential level.
In this state, the cell repair circuit conducts a normal operation or a repair operation in accordance with an input address generated from a predecoder coupled thereto. For the normal operation, the node A should be maintained in a "high" potential state. On the other hand, the node A should be maintained in a "low" potential state for the repair operation.
For the repair operation, it is necessary to establish a current path for flowing current from the node A to the ground because the initial state of the node A corresponds to a "high" potential level.
That is, in the case of an independent input address group "ax23&lt;0:3&gt;", the input address "ax23&lt;0&gt;" should have a "high" potential level. In the case of an independent input address group "ax45&lt;0:3&gt;", the input address "ax45&lt;1&gt;" should have a "high" potential level. In the case of an independent input address group "ax67&lt;0:3&gt;", the input address "ax67&lt;2&gt;" should have a "high" potential level.
In the configuration of FIG. 2, however, the repair operation is enabled by not only an input address selecting all the three programmed antifuses, but also by an input address selecting one of those programmed antifuses.
This is contrary to the system in which a repair operation is carried out only when all antifuses programmed for all independent input address groups are selected. As a result, a repair operation for cells requiring no repair may be carried out, thereby resulting in a malfunction of the system.
In order to solve problems involved in the circuit of FIG. 2, a cell repair circuit modified from that of FIG. 2 has been proposed. Examples associated with such a cell repair circuit are illustrated in FIGS. 3 and 4, respectively.
In the cell repair circuit shown in FIG. 3, power separation is made for each circuit part including one programmed antifuse. Signals generated from respective circuit parts as a result of the power separation are input to an AND gate which, in turn, generates an output signal nrd. In this cell repair circuit, a redundancy operation is conducted when all input stages of the AND gate have a "high" level.
In other words, respective nodes A, B, and C of all circuit parts should have a "low" potential level for the redundancy operation. This state is obtained only when the input addresses "ax23&lt;0&gt;", "ax45&lt;1&gt;", and "ax67&lt;2&gt;" selecting respective programmed antifuses of all circuit parts have a "low" level.
In the case of FIG. 3, accordingly, there is no possibility of a malfunction of the system which may occur in the case of FIG. 2.
However, the cell repair circuit of FIG. 3 is problematic in that the entire area of the chip increases.
Typically, current semiconductor memory devices require cell repair circuits, each including five circuit parts due to an increased storage capacity thereof.
In such a case, five nodes are coupled into an AND gate. Such a circuit should be provided at each of the redundancy circuits which are typically several hundreds in number. For this reason, it is difficult to reduce the entire memory area.
In the case of the cell repair circuit shown in FIG. 4, a method is used in which antifuses to be selected are not intended to be programmed while the remaining antifuses are programmed.
For a redundancy operation of this circuit, a node A should be maintained in a "high" potential state.
This state is obtained only when all input addresses selecting respective antifuses not programmed have a "high" level.
In the circuit of FIG. 4, accordingly, there is no possibility of a malfunction of the system which may occur in the case of FIG. 2.
However, the cell repair circuit of FIG. 4 involves a problem in regard to reliability because a large number of antifuses should be programmed. For this reason, this circuit cannot provide the best solution. Furthermore, this circuit involves a degradation in the repair efficiency.